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diff --git a/SHARC/ComputeField.hs b/SHARC/ComputeField.hs
new file mode 100644
index 0000000..d82d75f
--- /dev/null
+++ b/SHARC/ComputeField.hs
@@ -0,0 +1,210 @@
+{-
+  This file is part of shark-disassembler.
+
+  Copyright (C) 2014 Ricardo Wurmus
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-}
+
+{-# LANGUAGE QuasiQuotes #-}
+
+module SHARC.ComputeField where
+
+import           SHARC.Types
+import           SHARC.Word48
+
+import           Language.Literals.Binary
+import           Data.Map (fromList, findWithDefault)
+import           Data.Word (Word8, Word16, Word64)
+import           Data.Bits ((.&.), (.|.), shift, shiftL, shiftR)
+import           Text.Printf (printf)
+
+{-
+The Compute Field
+
+See page 6-1 for full description.
+
+The compute field of an instruction is 23 bit wide and structured like this:
+
+1 unused bit
+2 CU bits (00=ALU, 01=Multiplier, 10=Shifter)
+8 bit opcode
+3 register addresses (result, x operand, y operand), each 4 bit wide
+-}
+
+-- 23 bit compute field
+data ComputeField = ComputeField
+                    { compFieldCU     :: ComputationUnit
+                    , compFieldOpCode :: OpCode
+                    , compFieldRn     :: Dreg
+                    , compFieldRx     :: Dreg
+                    , compFieldRy     :: Dreg
+                    }
+
+data ComputationUnit = ALU | Multiplier | Shifter deriving Show
+type OpCode = Word8
+
+mkComputeField :: Word48 -> ComputeField
+mkComputeField w = ComputeField cu op rn rx ry
+  where
+    word64 = word48ToWord64 w
+    w' = word64 `cutMask` 0x000000FFFFFF
+    cu = case w' `cutMask` [b| 011 0000 0000 0000 0000 0000 |] of
+      0 -> ALU
+      1 -> Multiplier
+      2 -> Shifter
+    op = w' `cutMask` [b| 000 1111 1111 0000 0000 0000 |]
+    rn = mkDreg $ w' `cutMask` [b| 000 0000 0000 1111 0000 0000 |]
+    rx = mkDreg $ w' `cutMask` [b| 000 0000 0000 0000 1111 0000 |]
+    ry = mkDreg $ w' `cutMask` [b| 000 0000 0000 0000 0000 1111 |]
+
+instance Show ComputeField where
+  show cf = printer rn rx ry
+    where
+      dict = case compFieldCU cf of
+        ALU        -> opCodesALU
+        Multiplier -> opCodesMultiplier
+        Shifter    -> opCodesShifter
+      rn = show (compFieldRn cf)
+      rx = show (compFieldRx cf)
+      ry = show (compFieldRy cf)
+      def = rawPrintCF (show (compFieldCU cf)) (compFieldOpCode cf)
+      rawPrintCF cu op rn rx ry = printf "[%s] %s = %s [0x%02X] %s" cu rn rx op ry
+      printer = findWithDefault def (compFieldOpCode cf) dict
+
+-- special type for Type 6 instruction
+type ShiftOp = Word8
+data ImmediateShift = ImmediateShift
+                      ShiftOp {-6 bits-}
+                      Word16 {-dependent on shiftop: either 6 bit shift value + 6 bit length; or 8 bit value-}
+                      Dreg {-4 bit Rn register-}
+                      Dreg {-4 bit Rx register-}
+
+-- TODO
+instance Show ImmediateShift where
+  show (ImmediateShift op dat rn rx) =
+    "[" ++ show rn ++ " = " ++ printf "0x%02X" op ++ " " ++ show rx ++ " data:" ++ printf "0x%02X" dat ++ "]"
+
+
+
+opCodesALU = fromList
+  -- fixed point ALU operations (table 6-1)
+  [ (0, \n x y -> "") -- print nothing if the opcode is empty
+  , ([b| 0000 0001 |], \n x y -> n ++ " = " ++ x ++ " + " ++ y)                -- Rn = Rx + Ry
+  , ([b| 0000 0010 |], \n x y -> n ++ " = " ++ x ++ " - " ++ y)                -- Rn = Rx – Ry
+  , ([b| 0000 0101 |], \n x y -> n ++ " = " ++ x ++ " + " ++ y ++ " + CI")     -- Rn = Rx + Ry + CI
+  , ([b| 0000 0110 |], \n x y -> n ++ " = " ++ x ++ " - " ++ y ++ " + CI - 1") -- Rn = Rx – Ry + CI – 1
+  , ([b| 0000 1001 |], \n x y -> n ++ " = (" ++ x ++ " + " ++ y ++ ")/2")      -- Rn = (Rx + Ry)/2
+  , ([b| 0000 1010 |], \n x y -> "COMP("  ++ x ++ ", " ++ y ++ ")")            -- COMP(Rx, Ry)
+  , ([b| 0000 1011 |], \n x y -> "COMPU(" ++ x ++ ", " ++ y ++ ")")            -- COMPU(Rx, Ry)
+  , ([b| 0010 0101 |], \n x y -> n ++ " = " ++ x ++ " + CI")                   -- Rn = Rx + CI
+  , ([b| 0010 0110 |], \n x y -> n ++ " = " ++ x ++ " + CI - 1")               -- Rn = Rx + CI – 1
+  , ([b| 0010 1001 |], \n x y -> n ++ " = " ++ x ++ " + 1")                    -- Rn = Rx + 1
+  , ([b| 0010 1010 |], \n x y -> n ++ " = " ++ x ++ " - 1")                    -- Rn = Rx – 1
+  , ([b| 0010 0010 |], \n x y -> n ++ " = - " ++ x)                            -- Rn = – Rx
+  , ([b| 0011 0000 |], \n x y -> n ++ " = ABS " ++ x)                          -- Rn = ABS Rx
+  , ([b| 0010 0001 |], \n x y -> n ++ " = PASS " ++ x)                         -- Rn = PASS Rx
+  , ([b| 0100 0000 |], \n x y -> n ++ " = " ++ x ++ " AND " ++ y)              -- Rn = Rx AND Ry
+  , ([b| 0100 0001 |], \n x y -> n ++ " = " ++ x ++ " OR " ++ y)               -- Rn = Rx OR Ry
+  , ([b| 0100 0010 |], \n x y -> n ++ " = " ++ x ++ " XOR " ++ y)              -- Rn = Rx XOR Ry
+  , ([b| 0100 0011 |], \n x y -> n ++ " = NOT " ++ x)                          -- Rn = NOT Rx
+  , ([b| 0110 0001 |], \n x y -> n ++ " = MIN(" ++ x ++ ",  " ++ y ++ ")")     -- Rn = MIN(Rx, Ry)
+  , ([b| 0110 0010 |], \n x y -> n ++ " = MAX(" ++ x ++ ", " ++ y ++ ")")      -- Rn = MAX(Rx, Ry)
+  , ([b| 0110 0011 |], \n x y -> n ++ " = CLIP " ++ x ++ " BY " ++ y)          -- Rn = CLIP Rx BY Ry
+  -- floating-point ALU operations (table 6-2)
+  , ([b| 1000 0001 |], \n x y -> n ++ " = " ++ x ++ " + " ++ y)                -- Fn = Fx + Fy
+  , ([b| 1000 0010 |], \n x y -> n ++ " = " ++ x ++ " - " ++ y)                -- Fn = Fx – Fy
+  , ([b| 1001 0001 |], \n x y -> n ++ " = ABS (" ++ x ++ " + " ++ y ++ ")")    -- Fn = ABS (Fx + Fy)
+  , ([b| 1001 0010 |], \n x y -> n ++ " = ABS (" ++ x ++ " - " ++ y ++ ")")    -- Fn = ABS (Fx – Fy)
+  , ([b| 1000 1001 |], \n x y -> n ++ " = (" ++ x ++ " + " ++ y ++ ")/2")      -- Fn = (Fx + Fy)/2
+  , ([b| 1000 1010 |], \n x y -> n ++ " = COMP(" ++ x ++ ", " ++ y ++ ")")     -- Fn = COMP(Fx, Fy)
+  , ([b| 1010 0010 |], \n x y -> n ++ " = -" ++ x)                             -- Fn = –Fx
+  , ([b| 1011 0000 |], \n x y -> n ++ " = ABS " ++ x)                          -- Fn = ABS Fx
+  , ([b| 1010 0001 |], \n x y -> n ++ " = PASS " ++ x)                         -- Fn = PASS Fx
+  , ([b| 1010 0101 |], \n x y -> n ++ " = RND " ++ x)                          -- Fn = RND Fx
+  , ([b| 1011 1101 |], \n x y -> n ++ " = SCALB " ++ x ++ " BY " ++ y)         -- Fn = SCALB Fx BY Ry
+  , ([b| 1010 1101 |], \n x y -> n ++ " = MANT " ++ x)                         -- Rn = MANT Fx
+  , ([b| 1100 0001 |], \n x y -> n ++ " = LOGB " ++ x)                         -- Rn = LOGB Fx
+  , ([b| 1101 1001 |], \n x y -> n ++ " = FIX " ++ x ++ " BY " ++ y)           -- Rn = FIX Fx BY Ry
+  , ([b| 1100 1001 |], \n x y -> n ++ " = FIX " ++ x)                          -- Rn = FIX Fx
+  , ([b| 1101 1101 |], \n x y -> n ++ " = TRUNC " ++ x ++ " BY " ++ y)         -- Rn = TRUNC Fx BY Ry
+  , ([b| 1100 1101 |], \n x y -> n ++ " = TRUNC " ++ x)                        -- Rn = TRUNC Fx
+  , ([b| 1101 1010 |], \n x y -> n ++ " = FLOAT " ++ x ++ " BY " ++ y)         -- Fn = FLOAT Rx BY Ry
+  , ([b| 1100 1010 |], \n x y -> n ++ " = FLOAT " ++ x)                        -- Fn = FLOAT Rx
+  , ([b| 1100 0100 |], \n x y -> n ++ " = RECIPS " ++ x)                       -- Fn = RECIPS Fx
+  , ([b| 1100 0101 |], \n x y -> n ++ " = RSQRTS " ++ x)                       -- Fn = RSQRTS Fx
+  , ([b| 1110 0000 |], \n x y -> n ++ " = " ++ x ++ " COPYSIGN " ++ y)         -- Fn = Fx COPYSIGN Fy
+  , ([b| 1110 0001 |], \n x y -> n ++ " = MIN(" ++ x ++ ", " ++ y ++ ")")      -- Fn = MIN(Fx, Fy)
+  , ([b| 1110 0010 |], \n x y -> n ++ " = MAX(" ++ x ++ ", " ++ y ++ ")")      -- Fn = MAX(Fx, Fy)
+  , ([b| 1110 0011 |], \n x y -> n ++ " = CLIY " ++ x ++ " BY " ++ y)          -- Fn = CLIP Fx BY Fy
+  ]
+
+
+opCodesMultiplier = fromList []  -- TODO
+{-
+-- fixed-point multiplier operations (table 6-3)
+-- TODO: check table 6-5 and table 6-6 for y/x/f/r flags
+[b| 01yx f00r ] -- on page 6-56 -- Rn = Rx*Ry mod2
+[b| 01yx f10r ] -- on page 6-56 -- MRF = Rx*Ry mod2
+[b| 01yx f11r ] -- on page 6-56 -- MRB = Rx*Ry mod2
+[b| 10yx f00r ] -- on page 6-57 -- Rn = MRF +Rx*Ry mod2
+[b| 10yx f01r ] -- on page 6-57 -- Rn = MRB +Rx*Ry mod2
+[b| 10yx f10r ] -- on page 6-57 -- MRF = MRF +Rx*Ry mod2
+[b| 10yx f11r ] -- on page 6-57 -- MRB = MRB +Rx*Ry mod2
+[b| 11yx f00r ] -- on page 6-58 -- Rn = MRF –Rx*Ry mod2
+[b| 11yx f01r ] -- on page 6-58 -- Rn = MRB –Rx*Ry mod2
+[b| 11yx f10r ] -- on page 6-58 -- MRF = MRF –Rx*Ry mod2
+[b| 11yx f11r ] -- on page 6-58 -- MRB = MRB –Rx*Ry mod2
+[b| 0000 f00x ] -- on page 6-59 -- Rn = SAT MRF mod1
+[b| 0000 f01x ] -- on page 6-59 -- Rn = SAT MRB mod1
+[b| 0000 f10x ] -- on page 6-59 -- MRF = SAT MRF mod1
+[b| 0000 f11x ] -- on page 6-59 -- MRB = SAT MRB mod1
+[b| 0001 100x ] -- on page 6-60 -- Rn =RND MRF mod1
+[b| 0001 101x ] -- on page 6-60 -- Rn = RND MRB mod1
+[b| 0001 110x ] -- on page 6-60 -- MRF = RND MRF mod1
+[b| 0001 111x ] -- on page 6-60 -- MRB = RND MRB mod1
+[b| 0001 0100 ] -- on page 6-61 -- MRF = 0
+[b| 0001 0110r ] -- on page 6-61 -- MRB = 0
+-- MR = Rn on page 6-62
+-- Rn = MR on page 6-62
+
+-- floating-point multiplier operations (table 6-4)
+[b| 0011 0000 ] -- on page 6-64 -- Fn = Fx*Fy
+-}
+
+
+opCodesShifter = fromList
+  -- shifter operations (table 6-8)
+  [ ([b| 0000 0000 |], \n x y -> n ++ " = LSHIFT " ++ x ++ " BY " ++ y)               -- Rn = LSHIFT Rx BY Ry|<data8>
+  , ([b| 0010 0000 |], \n x y -> n ++ " = OR LSHIFT " ++ x ++ " BY " ++ y)            -- Rn = Rn OR LSHIFT Rx BY Ry|<data8>
+  , ([b| 0000 0100 |], \n x y -> n ++ " = ASHIFT " ++ x ++ " BY " ++ y)               -- Rn = ASHIFT Rx BY Ry|<data8>
+  , ([b| 0010 0100 |], \n x y -> n ++ " = " ++ n ++ " OR ASHIFT " ++ x ++ " BY "++ y) -- Rn = Rn OR ASHIFT Rx BY Ry|<data8>
+  , ([b| 0000 1000 |], \n x y -> n ++ " = ROT " ++ x ++ " BY " ++ y)                  -- Rn = ROT Rx BY Ry|<data8>
+  , ([b| 1100 0100 |], \n x y -> n ++ " = BCLR " ++ x ++ " BY " ++ y)                 -- Rn = BCLR Rx BY Ry|<data8>
+  , ([b| 1100 0000 |], \n x y -> n ++ " = BSET " ++ x ++ " BY " ++ y)                 -- Rn = BSET Rx BY Ry|<data8>
+  , ([b| 1100 1000 |], \n x y -> n ++ " = BTGL " ++ x ++ " BY " ++ y)                 -- Rn = BTGL Rx BY Ry|<data8>
+  , ([b| 1100 1100 |], \n x y -> "BTST " ++ x ++ " BY " ++ y)                         -- BTST Rx BY Ry|<data8>
+  , ([b| 0100 0100 |], \n x y -> n ++ " = FDEP " ++ x ++ " BY " ++ y)                 -- Rn = FDEP Rx BY Ry|<bit6>:<len6>
+  , ([b| 0110 0100 |], \n x y -> n ++ " = " ++ n ++ " OR FDEP " ++ x ++ " BY " ++ y)  -- Rn = Rn OR FDEP Rx BY Ry|<bit6>:<len6>
+  , ([b| 0100 1100 |], \n x y -> n ++ " = FDEP " ++ x ++ " BY " ++ y)                 -- Rn = FDEP Rx BY Ry|<bit6>:<len6> (SE)
+  , ([b| 0110 1100 |], \n x y -> n ++ " = " ++ n ++ " OR FDEP " ++ x ++ " BY " ++ y)  -- Rn = Rn OR FDEP Rx BY Ry|<bit6>:<len6>(SE)
+  , ([b| 0100 0000 |], \n x y -> n ++ " = FEXT " ++ x ++ " BY " ++ y)                 -- Rn = FEXT RX BY Ry|<bit6>:<len6>
+  , ([b| 0100 1000 |], \n x y -> n ++ " = FEXT " ++ x ++ " BY " ++ y ++ " (SE)")      -- Rn = FEXT Rx BY Ry|<bit6>:<len6> (SE)
+  , ([b| 1000 0000 |], \n x y -> n ++ " = EXP " ++ x)                                 -- Rn = EXP Rx
+  , ([b| 1000 0100 |], \n x y -> n ++ " = EXP " ++ x ++ " (EX)")                      -- Rn = EXP Rx (EX)
+  , ([b| 1000 1000 |], \n x y -> n ++ " = LEFTZ " ++ x)                               -- Rn = LEFTZ Rx
+  , ([b| 1000 1100 |], \n x y -> n ++ " = LEFTO " ++ x)                               -- Rn = LEFTO Rx
+  , ([b| 1001 0000 |], \n x y -> n ++ " = FPACK " ++ x)                               -- Rn = FPACK Fx
+  , ([b| 1001 0100 |], \n x y -> n ++ " = FUNPACK " ++ x)                             -- Fn = FUNPACK Rx
+  ]
diff --git a/SHARC/Instruction.hs b/SHARC/Instruction.hs
new file mode 100644
index 0000000..5c3b1bf
--- /dev/null
+++ b/SHARC/Instruction.hs
@@ -0,0 +1,500 @@
+{-
+  This file is part of shark-disassembler.
+
+  Copyright (C) 2014 Ricardo Wurmus
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-}
+
+{-# LANGUAGE QuasiQuotes #-}
+
+module SHARC.Instruction where
+
+import           SHARC.Types
+import           SHARC.Word48
+import           SHARC.ComputeField
+
+import           Language.Literals.Binary
+import           Data.Bits ((.&.), (.|.), xor, shift, shiftL, shiftR, testBit)
+import           Data.Word
+import           Data.List (intercalate)
+import           Text.Printf (printf)
+import           Data.Binary.Get
+
+
+data Instruction = Type1 Word48
+                 | Type2 Cond ComputeField
+                 | Type3
+                   Cond
+                   ComputeField
+                   Ireg
+                   Mreg
+                   Ureg
+                   AccessType
+                   Memory
+                   WordAccess
+                   Update
+                 | Type4
+                   Cond
+                   ComputeField
+                   Word8 {-6 bit data-}
+                   Dreg
+                   Ireg
+                   AccessType
+                   Memory
+                   Update
+                 | Type5Transfer
+                   Cond
+                   ComputeField
+                   Ureg {-source register, 7 bit-}
+                   Ureg {-destination register, 7 bit-}
+                 | Type5Swap
+                   Cond
+                   ComputeField
+                   Dreg {-x, 4 bit-}
+                   Dreg {-y, 4 bit-}
+                 | Type6WithDataAccess -- with data access
+                   Cond
+                   ImmediateShift
+                   Dreg
+                   Ireg
+                   Mreg
+                   AccessType
+                   Memory
+                 | Type6WithoutDataAccess -- without data access
+                   Cond
+                   ImmediateShift
+                 | Type7 Word48
+                 | Type8
+                   BranchType
+                   Cond
+                   Address24
+                   Bool {-loop abort-}
+                   Bool {-branch delayed or not-}
+                   Bool {-clear interrupt-}
+                 | Type9 Word48
+                 | Type10 Word48
+                 | Type11
+                   ReturnSource {- subroutine or interrupt -}
+                   Cond
+                   Bool {-return delayed or not-}
+                   Bool {-else clause used or not-}
+                   Bool {-loop reentry modifier specified or not-}
+                   ComputeField
+                 | Type12Ureg Ureg Address24
+                 | Type12Immediate Word16 Address24
+                 | Type13 TermCond Address24
+                 | Type14 AccessType Memory WordAccess Ureg Address32
+                 | Type15 Word48
+                 | Type16 Word48
+                 | Type17 Ureg Word32
+                 | Type18 BitOp Sreg Word32
+                 | Type19 Word48
+                 | Type20
+                   ([String], [String]) {-list of pushes and pops-}
+                   Bool    {-cause a cash flush-}
+                 | NOP  -- Type 21
+                 | IDLE -- Type 22
+                 | Type25 Word48
+                 | UndefinedInstruction Word48
+                 | InvalidInstruction Word48
+
+instance Show Instruction where
+  show NOP  = "NOP"
+  show IDLE = "IDLE"
+  show (UndefinedInstruction w) = "!! UNDEFINED: " ++ show w
+  show (InvalidInstruction w)   = "!! INVALID: " ++ show w
+  show t = let f = printf "%-46s; %s" in case t of
+    Type1 w                  -> f (showType1 w) "type 1"
+    Type2{}                  -> f (showType2 t) "type 2"
+    Type3{}                  -> f (showType3 t) "type 3"
+    Type4{}                  -> f (showType4 t) "type 4"
+    Type5Transfer{}          -> f (showType5 t) "type 5 (transfer)"
+    Type5Swap{}              -> f (showType5 t) "type 5 (swap)"
+    Type6WithDataAccess{}    -> f (showType6 t) "type 6 (with data access)"
+    Type6WithoutDataAccess{} -> f (showType6 t) "type 6 (without data access)"
+    Type7 w                  -> f (showType7 w) "type 7"
+    Type8{}                  -> f (showType8 t) "type 8"
+    Type9 w                  -> f (showType9 w) "type 9"
+    Type10 w                 -> f (showType10 w) "type 10"
+    Type11{}                 -> f (showType11 t) "type 11"
+    Type12Immediate{}        -> f (showType12 t) "type 12 (immediate)"
+    Type12Ureg{}             -> f (showType12 t) "type 12 (from ureg)"
+    Type13{}                 -> f (showType13 t) "type 13"
+    Type14{}                 -> f (showType14 t) "type 14"
+    Type15 w                 -> f (showType15 w) "type 15"
+    Type16 w                 -> f (showType16 w) "type 16"
+    Type17{}                 -> f (showType17 t) "type 17"
+    Type18{}                 -> f (showType18 t) "type 18"
+    Type19 w                 -> f (showType19 w) "type 19"
+    Type20{}                 -> f (showType20 t) "type 20"
+    Type25 w                 -> f (showType25 w) "type 25"
+
+
+showType1 w = "  TODO: " ++ show w
+
+showType2 (Type2 cond cf) = show cond ++ show cf
+
+showType3 (Type3 cond compute ireg mreg ureg rw mem wa up) =
+  show cond ++ show compute ++ assignment ++ flag
+  where
+    imOrder = case up of
+               PreModify -> [show mreg, show ireg]
+               PostModify -> [show ireg, show mreg]
+    pair = "(" ++ intercalate ", " imOrder ++ ")"
+    mem' = case mem of
+      Prog -> "PM" ++ pair
+      Data -> "DM" ++ pair
+    assignment = case rw of
+      Read  -> show ureg ++ "=" ++ mem'
+      Write -> mem' ++ "=" ++ show ureg
+    flag = case wa of
+      LW -> " (LW)"
+      _ -> ""
+
+showType4 (Type4 cond compute dat dreg ireg rw mem up) =
+  show cond ++ show compute ++ assignment
+  where
+    -- print 6 bit data as two's complement
+    dat' = if dat `testBit` 5
+           then '-' : show (dat `xor` 0x3F)
+           else show dat
+    order = case up of
+      PreModify -> [dat', show ireg]
+      PostModify -> [show ireg, dat']
+    pair = "(" ++ intercalate ", " order ++ ")"
+    mem' = case mem of
+      Prog -> "PM" ++ pair
+      Data -> "DM" ++ pair
+    assignment = case rw of
+      Read  -> show dreg ++ "=" ++ mem'
+      Write -> mem' ++ "=" ++ show dreg
+
+showType5 (Type5Transfer cond compute src dest) =
+  optional ++ sep ++ show dest ++ "=" ++ show src
+  where
+    optional = show cond ++ show compute
+    sep = if optional == "" then "" else ", "
+showType5 (Type5Swap cond compute x y) =
+  optional ++ sep ++ show x ++ "<->" ++ show y
+  where
+    optional = show cond ++ show compute
+    sep = if optional == "" then "" else ", "
+
+showType6 (Type6WithDataAccess cond shiftField dreg ireg mreg rw mem) =
+  show cond ++ show shiftField ++ assignment
+  where
+    pair = "(" ++ intercalate ", " [show ireg, show mreg] ++ ")"
+    mem' = case mem of
+      Prog -> "PM" ++ pair
+      Data -> "DM" ++ pair
+    assignment = case rw of
+      Read  -> show dreg ++ "=" ++ mem'
+      Write -> mem' ++ "=" ++ show dreg
+
+showType6 (Type6WithoutDataAccess cond shiftField) =
+  show cond ++ show shiftField
+
+showType7 w = "  TODO: " ++ show w
+
+-- TODO: if Call, ignore LA and CI
+-- TODO: flag handling is ugly
+showType8 (Type8 t cond addr a d c) = show cond ++ t' ++ flags
+  where
+    t' = case t of
+      Jump -> "JUMP " ++ show addr
+      Call -> "CALL " ++ show addr
+    a' = if a then "LA" else ""
+    d' = if d then "DB" else ""
+    c' = if c then "CI" else ""
+    flags = if a || d || c
+            then " (" ++ intercalate ", " (filter (/= "") [a', d', c']) ++ ")"
+            else ""
+
+showType9 w = "  TODO: " ++ show w
+
+showType10 w = "  TODO: " ++ show w
+
+showType11 (Type11 rs cond d e l cf) = show cond ++ rs' ++ flags ++ elseCompute
+  where
+    rs' = case rs of
+      Subroutine -> "RTS"
+      Interrupt  -> "RTI"
+    -- TODO: this is ugly
+    d' = if d then "DB" else ""
+    l' = if l then "LR" else ""
+    flags = if d || l
+            then " (" ++ intercalate ", " (filter (/= "") [d', l']) ++ ")"
+            else ""
+    e' = if e then ", ELSE " else ", "
+    -- do not print at all if opcode in compute field is empty
+    -- TODO: can this be encoded in the type instead of doing an ugly string comparison?
+    elseCompute = if show cf == "" then "" else e' ++ show cf
+
+showType12 (Type12Immediate dat reladdr) =
+  "LNCTR=" ++ show dat ++ ", DO " ++ show reladdr ++ " UNTIL LCE"
+showType12 (Type12Ureg ureg reladdr) =
+  "LNCTR=" ++ show ureg ++ ", DO " ++ show reladdr ++ " UNTIL LCE"
+
+showType13 (Type13 term reladdr) =
+  "DO " ++ show reladdr ++ " UNTIL " ++ show term
+
+showType14 (Type14 rw mem wa ureg addr) = lhs ++ " = " ++ rhs ++ lwflag
+  where
+    lwflag = case wa of
+              LW -> " (LW)"
+              _ -> ""
+    memloc = case mem of
+              Data -> "DM(" ++ show addr ++ ")"
+              Prog -> "PM(" ++ show addr ++ ")"
+    lhs = case rw of
+           Write -> memloc
+           Read  -> show ureg
+    rhs = case rw of
+           Write -> show ureg
+           Read  -> memloc
+
+showType15 w = "  TODO: " ++ show w
+
+showType16 w = "  TODO: " ++ show w
+
+showType17 (Type17 ureg dat) = show ureg ++ " = " ++ printf "0x%08X" dat
+
+showType18 (Type18 bop sreg w) =
+  "BIT " ++ show bop ++ " " ++ show sreg ++ " " ++ printf "0x%08X" w
+
+showType19 w = "  TODO: " ++ show w
+
+showType20 (Type20 (pushes,pops) fc) = intercalate ", " (pu ++ po ++ [flush])
+  where
+    pu = map (\x -> "PUSH " ++ x) pushes
+    po = map (\x -> "POP "  ++ x) pops
+    flush = if fc then "FLUSH CACHE" else ""
+
+showType25 w = "  TODO: " ++ show w
+
+
+
+-- TODO
+parseType1 = Type1
+
+parseType2 w = Type2 cond (mkComputeField w)
+  where
+    cond = mkCond w
+
+parseType3 w = Type3 cond compute ireg mreg ureg rw mem wa up
+  where
+    w64 = word48ToWord64 w
+    cond = mkCond w
+    compute = mkComputeField w
+    ireg = mkIreg $ w64 `cutMask` [b| 000 0 111 000 00000 000 0000000 0000000 00000000 00000000 |]
+    mreg = mkMreg $ w64 `cutMask` [b| 000 0 000 111 00000 000 0000000 0000000 00000000 00000000 |]
+    ureg = mkUreg $ w64 `cutMask` [b| 000 0 000 000 00000 000 1111111 0000000 00000000 00000000 |]
+    rw   = if w64 `testBit` 31 then Read else Write
+    mem  = if w64 `testBit` 32 then Data else Prog
+    wa   = if w64 `testBit` 30 then LW else NW
+    up   = if w64 `testBit` 44 then PostModify else PreModify
+
+parseType4 w = Type4 cond compute dat dreg ireg rw mem up
+  where
+    w64 = word48ToWord64 w
+    cond = mkCond w
+    compute = mkComputeField w
+    dat  = w64 `cutMask` 0x0001F8000000
+    dreg = mkDreg $ w64 `cutMask` 0x000007800000
+    ireg = mkIreg $ w64 `cutMask` [b| 000 0 111 000 00000 000 0000000 0000000 00000000 00000000 |]
+    rw   = if w64 `testBit` 39 then Read else Write
+    mem  = if w64 `testBit` 40 then Data else Prog
+    up   = if w64 `testBit` 38 then PostModify else PreModify
+
+parseType5 w = if w64 `testBit` 43
+               then let
+                 x = mkDreg $ w64 `cutMask` 0x000007800000
+                 y = mkDreg $ w64 `cutMask` 0x03C000000000
+                 in Type5Swap cond compute x y
+               else let
+                 src  = mkUreg $ ((w64 `cutMask` 0x07C000000000) `shiftL` 2) .|. (w64 `cutMask` 0x000180000000)
+                 dest = mkUreg $ w64 `cutMask` 0x00003F800000
+                 in Type5Transfer cond compute src dest
+  where
+    w64 = word48ToWord64 w
+    cond = mkCond w
+    compute = mkComputeField w
+
+parseType6 w = if w64 `testBit` 47
+               then let -- with data access
+                 dreg = mkDreg $ w64 `cutMask` [b| 0000 000 000 00000 00 0000 1111 0 000000 00000000 0000 0000 |]
+                 ireg = mkIreg $ w64 `cutMask` [b| 0000 111 000 00000 00 0000 0000 0 000000 00000000 0000 0000 |]
+                 mreg = mkMreg $ w64 `cutMask` [b| 0000 000 111 00000 00 0000 0000 0 000000 00000000 0000 0000 |]
+                 rw   = if w64 `testBit` 31 then Read else Write
+                 mem  = if w64 `testBit` 32 then Data else Prog
+                 in
+                  Type6WithDataAccess cond shiftField dreg ireg mreg rw mem
+               else -- without data access
+                 Type6WithoutDataAccess cond shiftField
+  where
+    w64 = word48ToWord64 w
+    cond = mkCond w
+    shiftField = ImmediateShift op dat rn rx
+    op  = w64 `cutMask` 0x0000003F0000
+    dat = (w64 `cutMask` 0x000078000000) `shiftL` 8 .|. (w64 `cutMask` 0x00000000FF00)
+    rn = Dreg $ w64 `cutMask` 0xF0
+    rx = Dreg $ w64 `cutMask` 0x0F
+
+-- TODO
+parseType7 = Type7
+
+parseType8 :: (Word32 -> Address24) -> Word48 -> Instruction
+parseType8 addressConstr w = Type8 t cond addr a d c
+  where
+    w64 = word48ToWord64 w
+    t = if w64 `testBit` 39 then Jump else Call
+    cond = mkCond w
+    addr = addressConstr $ w64 `cutMask` 0x000000FFFFFF
+    a = w64 `testBit` 38 -- loop abort
+    d = w64 `testBit` 26 -- branch delayed or not
+    c = w64 `testBit` 24 -- clear interrupt
+
+-- TODO
+parseType9 = Type9
+
+-- TODO
+parseType10 = Type10
+
+parseType11 rs w = Type11 rs cond d e l cf where
+    cond = mkCond w
+    w64 = word48ToWord64 w
+    d = w64 `testBit` 26 -- return delayed
+    e = w64 `testBit` 25 -- else clause
+    l = w64 `testBit` 24 -- loop reentry
+    cf = mkComputeField w
+
+parseType12 w = if w64 `testBit` 40
+                then let -- loop counter load from a Ureg
+                  ureg = mkUreg $ w64 `cutMask` 0x007F00000000
+                  in Type12Ureg ureg reladdr
+                else let -- immediate loop counter load
+                  dat = w64 `cutMask` 0x00FFFF000000
+                  in Type12Immediate dat reladdr
+  where
+    w64 = word48ToWord64 w
+    reladdr = RelAddress24 $ w64 `cutMask` 0xFFFFFF -- lowest 24 bit
+
+parseType13 w = Type13 term reladdr
+  where
+    w64 = word48ToWord64 w
+    term = mkTermCond w
+    reladdr = RelAddress24 $ w64 `cutMask` 0xFFFFFF -- lowest 24 bit
+
+parseType14 w = Type14 rw mem wa ureg addr
+  where
+    w64 = word48ToWord64 w
+    rw   = if w64 `testBit` 40 then Read else Write
+    mem  = if w64 `testBit` 41 then Data else Prog
+    wa   = if w64 `testBit` 39 then LW   else NW
+    ureg = mkUreg $ w64 `cutMask` 0x00EF00000000
+    addr = Address32 $ w64 `cutMask` 0x0000FFFFFFFF
+
+-- TODO
+parseType15 = Type15
+parseType16 = Type16
+
+parseType17 w = Type17 ureg dat
+  where
+    w64 = word48ToWord64 w
+    dat = w64 `cutMask` 0x0000FFFFFFFF
+    ureg = mkUreg $ w64 `cutMask` 0x00EF00000000
+
+parseType18 w = Type18 bop sreg dat
+  where
+    w64 = word48ToWord64 w
+    dat = w64 `cutMask` 0x0000FFFFFFFF
+    bop = [ SET, CLR, TGL, TST, XOR ] !! (w64 `cutMask` 0x00E000000000)
+    sreg = mkSreg $ w64 `cutMask` 0x00FF00000000
+
+-- TODO
+parseType19 = Type19
+
+parseType20 w = Type20 (pushes, pops) fc
+  where
+    w64 = word48ToWord64 w
+    lpu = if w64 `testBit` 39 then "LOOP"  else ""
+    lpo = if w64 `testBit` 38 then "LOOP"  else ""
+    spu = if w64 `testBit` 37 then "STS"   else ""
+    spo = if w64 `testBit` 36 then "STS"   else ""
+    ppu = if w64 `testBit` 35 then "PCSTK" else ""
+    ppo = if w64 `testBit` 34 then "PCSTK" else ""
+    pushes = filter (/= "") [lpu, spu, ppu]
+    pops = filter (/= "") [lpo, spo, ppo]
+    fc = w64 `testBit` 33
+
+-- TODO
+parseType25 = Type25
+
+
+parseInstruction :: Word48 -> Instruction
+parseInstruction word =
+  let
+    w64 = word48ToWord64 word
+    b1 = (w64 `cutMask` 0xFF0000000000) :: Word8
+    b2 = (w64 `cutMask` 0x00FF00000000) :: Word8
+  in case fromIntegral b1 of
+   [b| 0000 0000 |] -> if b2 `testBit` 7
+                       then IDLE
+                       else NOP
+   [b| 0000 0001 |] -> parseType2 word
+   [b| 0000 0010 |] -> parseType6 word
+   [b| 0000 0011 |] -> UndefinedInstruction word
+   [b| 0000 0100 |] -> parseType7 word
+   [b| 0000 0101 |] -> UndefinedInstruction word
+   [b| 0000 0110 |] -> parseType8 Address24 word
+   [b| 0000 0111 |] -> parseType8 RelAddress24 word
+   [b| 0000 1000 |] -> parseType9 word
+   [b| 0000 1001 |] -> parseType9 word
+   [b| 0000 1010 |] -> parseType11 Subroutine word
+   [b| 0000 1011 |] -> parseType11 Interrupt word
+   [b| 0000 1100 |] -> parseType12 word
+   [b| 0000 1101 |] -> parseType12 word
+   [b| 0000 1110 |] -> parseType13 word
+   [b| 0000 1111 |] -> parseType17 word
+
+   [b| 0001 0100 |] -> parseType18 word
+   [b| 0001 0101 |] -> UndefinedInstruction word
+   [b| 0001 0110 |] -> parseType19 word
+   [b| 0001 0111 |] -> parseType20 word
+   [b| 0001 1000 |] -> parseType25 word
+
+   -- check six bit prefix
+   _ -> case b1 .&. 0xFC of
+     [b| 0001 0000 |] -> parseType14 word
+     -- check four bit prefix
+     _ -> case b1 .&. 0xF0 of
+       [b| 0110 0000 |] -> parseType4 word
+       [b| 0111 0000 |] -> parseType5 word
+       [b| 1000 0000 |] -> parseType6 word
+       [b| 1001 0000 |] -> parseType16 word
+       -- check three bit prefix
+       _ -> case b1 .&. 0xE0 of
+         [b| 001 00000 |] -> parseType1 word
+         [b| 010 00000 |] -> parseType3 word
+         [b| 101 00000 |] -> parseType15 word
+         [b| 110 00000 |] -> parseType10 word
+         [b| 111 00000 |] -> parseType10 word
+         _ -> InvalidInstruction word
+
+getInstruction :: Get Instruction
+getInstruction = fmap parseInstruction getPackedWord48
+
+printInstructionWithAddr :: (Word64, Instruction) -> IO ()
+printInstructionWithAddr (addr, instr) = printf "0x%05X: %s\n" addr (show instr)
diff --git a/SHARC/Kernel.hs b/SHARC/Kernel.hs
new file mode 100644
index 0000000..c074f36
--- /dev/null
+++ b/SHARC/Kernel.hs
@@ -0,0 +1,51 @@
+{-
+  This file is part of shark-disassembler.
+
+  Copyright (C) 2014 Ricardo Wurmus
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-}
+
+{-# LANGUAGE OverloadedStrings #-}
+
+module SHARC.Kernel where
+
+import           SHARC.Types
+import           SHARC.Word48
+import           SHARC.Instruction
+
+import           Control.Monad (replicateM,mapM_)
+import           Data.Word (Word64)
+import           Data.Binary.Get
+import qualified Data.ByteString.Lazy as B
+
+
+type Kernel = [Instruction]
+
+-- the boot kernel is 256 48-bit words long,
+-- each 48-bit is read as six 8-bit packages (LSB first)
+getKernel :: Get Kernel
+getKernel = replicateM 256 getInstruction
+
+parseKernel :: B.ByteString -> Kernel
+parseKernel = runGet getKernel
+
+-- p.609, hw.pdf
+-- ivt_start_address = 0x90000 :: Word64
+-- ivt_end_address   = 0x900ff :: Word64
+printKernel :: B.ByteString -> IO ()
+printKernel bs = mapM_ printInstructionWithAddr $ zip [offset..] kernel
+  where
+    offset = 0x90000 :: Word64
+    kernel = parseKernel bs
diff --git a/SHARC/Types.hs b/SHARC/Types.hs
new file mode 100644
index 0000000..47e4686
--- /dev/null
+++ b/SHARC/Types.hs
@@ -0,0 +1,184 @@
+{-
+  This file is part of shark-disassembler.
+
+  Copyright (C) 2014 Ricardo Wurmus
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-}
+
+module SHARC.Types where
+
+import           SHARC.Word48
+
+import           Data.Word
+import           Data.Map (fromList, findWithDefault)
+import           Data.Bits ((.&.), (.|.), xor, testBit, shift, shiftR)
+import           Text.Printf (printf)
+
+-- TODO: check other register assigments as well!  They may need to be shifted first.
+
+
+data Cond = Cond Word8
+-- the 5 bit condition codes are at an odd position in the byte, so we
+-- have to cut them out [ 00111110 ]
+-- TODO: valid values go from 0 to 31, restrict!
+mkCond :: Word48 -> Cond
+mkCond w = Cond $ w64 `cutMask` 0x003E00000000
+  where
+    w64 = word48ToWord64 w
+
+data TermCond = TermCond Word8
+-- the 5 bit condition codes are at an odd position in the byte, so we
+-- have to cut them out [ 00111110 ]
+-- TODO: valid values go from 0 to 31, restrict!
+mkTermCond :: Word48 -> TermCond
+mkTermCond w = TermCond $ w64 `cutMask` 0x003E00000000
+  where
+    w64 = word48ToWord64 w
+
+-- from table 1-4 (isr.pdf) "Conditional Execution Codes Summary"
+condCodes = [
+  "EQ",
+  "NE",
+  "GT",
+  "LT",
+  "GE",
+  "LE",
+  "AC",
+  "NOT AC",
+  "AV",
+  "NOT AV",
+  "MV",
+  "NOT MV",
+  "MS",
+  "NOT MS",
+  "SV",
+  "NOT SV",
+  "SZ",
+  "NOT SZ",
+  "TF",
+  "NOT TF",
+  "FLAG0_IN",
+  "NOT FLAG0_IN",
+  "FLAG1_IN",
+  "NOT FLAG1_IN",
+  "FLAG2_IN",
+  "NOT FLAG2_IN",
+  "FLAG3_IN",
+  "NOT FLAG3_IN",
+  "BM",
+  "NOT BM",
+  "NOT ICE",
+  "TRUE" ]
+
+condCodeMap = fromList $ zip [0..] condCodes
+termCodeMap = fromList $ zip [0..] $ (init . init) condCodes ++ ["LCE", "FOREVER"]
+
+instance Show Cond where
+  -- do not print if code is "TRUE" (31)
+  show (Cond n) = if n == 31 then ""
+                  else "IF " ++ findWithDefault (printf "0x%02X" n) n condCodeMap ++ " "
+
+instance Show TermCond where
+  show (TermCond n) = findWithDefault (printf "0x%02X" n) n termCodeMap
+
+
+data Ireg = Ireg Word8
+mkIreg :: Word8 -> Ireg
+mkIreg n = Ireg $ n .&. 0x07
+instance Show Ireg where
+  show (Ireg n) = printf "I%d" n
+
+data Mreg = Mreg Word8
+mkMreg :: Word8 -> Mreg
+mkMreg n = Mreg $ n .&. 0x07
+instance Show Mreg where
+  show (Mreg n) = printf "M%d" n
+
+-- TODO: see table 1-8 and 1-11 in isr.pdf
+-- 7 bit universal register
+data Ureg = Ureg Word8
+mkUreg :: Word8 -> Ureg
+mkUreg n = Ureg $ n .&. 0xEF
+instance Show Ureg where
+  show (Ureg n) = printf "0x%02X" n
+
+-- 4 bit system register
+data Sreg = Sreg Word8
+mkSreg :: Word8 -> Sreg
+mkSreg n = Sreg $ n .&. 0x0F
+instance Show Sreg where
+  show (Sreg n) = printf "0x%01X" n
+
+-- 4 bit data register
+data Dreg = Dreg Word8
+mkDreg :: Word8 -> Dreg
+mkDreg n = Dreg $ n .&. 0x0F
+instance Show Dreg where
+  show (Dreg n) = printf "R%d" n -- TODO: according to the docs this is R15-R0 *and* F15-F0
+
+data Address24 = Address24 Word32    -- absolute 24 bit address
+               | RelAddress24 Word32 -- relative 24 bit address
+data Address32 = Address32 Word32    -- absolute 32 bit address
+               | RelAddress32 Word32 -- relative 24 bit address
+
+instance Show Address24 where
+  show (Address24 w) = printf "0x%06X" w
+  show (RelAddress24 w) = printf "(PC,%s)" w' -- two's complement
+    where w' = if w `testBit` 23 then '-' : show (w `xor` 0xFFFFFF) else show w
+
+instance Show Address32 where
+  show (Address32 w) = printf "0x%08X" w
+  show (RelAddress32 w) = printf "(PC,%s)" w' -- two's complement
+    where w' = if w `testBit` 31 then '-' : show (w `xor` 0xFFFFFFFF) else show w
+
+
+toWord32 :: (Word8, Word8, Word8, Word8) -> Word32
+toWord32 (a,b,c,d) = fromIntegral a `shift` 24 .|.
+                     fromIntegral b `shift` 16 .|.
+                     fromIntegral c `shift`  8 .|.
+                     fromIntegral d
+
+data Update = PreModify -- 0, no update
+            | PostModify -- 1, with update
+
+-- TODO: check again Table 1-7 Opcode Acronyms to be sure that the mapping order is right!
+type PushPops = ([String], [String])
+
+data Memory = Data -- data memory
+            | Prog -- programme memory
+            deriving Show
+data AccessType = Read | Write  -- memory acces
+                deriving Show
+data WordAccess = NW | LW  -- LW forces a long word access when address is in normal word address
+                deriving Show
+
+data BranchAbsRel = Abs -- direct branch (absolute address)
+                  | Rel -- PC-relative branch
+                  deriving Show
+
+data BranchType = Jump
+                | Call
+                deriving Show
+
+data ReturnSource = Subroutine
+                  | Interrupt
+                  deriving Show
+
+data BitOp = SET
+           | CLR
+           | TGL
+           | TST
+           | XOR
+           deriving Show
diff --git a/SHARC/Word48.hs b/SHARC/Word48.hs
new file mode 100644
index 0000000..42e1075
--- /dev/null
+++ b/SHARC/Word48.hs
@@ -0,0 +1,58 @@
+{-
+  This file is part of shark-disassembler.
+
+  Copyright (C) 2014 Ricardo Wurmus
+
+  This program is free software: you can redistribute it and/or modify
+  it under the terms of the GNU General Public License as published by
+  the Free Software Foundation, either version 3 of the License, or
+  (at your option) any later version.
+
+  This program is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU General Public License for more details.
+
+  You should have received a copy of the GNU General Public License
+  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+-}
+
+module SHARC.Word48 where
+
+import           Text.Printf (printf)
+import           Data.Word (Word8, Word64)
+import           Data.Bits ((.&.), (.|.), shiftL, shiftR, testBit)
+import           Data.Binary.Get
+import           Control.Monad (replicateM)
+
+data Word48 = Word48 (Word8, Word8, Word8, Word8, Word8, Word8)
+instance Show Word48 where
+  show (Word48 (a,b,c,d,e,f)) =
+    unwords $ map (printf "0x%02X") [a,b,c,d,e,f]
+
+unpackWord8Word48 :: [Word8] -> Word48
+unpackWord8Word48 [a,b,c,d,e,f] = Word48 (f,e,d,c,b,a)
+
+getWord48 :: ([Word8] -> Word48) -> Get Word48
+getWord48 p = fmap p $ replicateM 6 getWord8
+
+getPackedWord48 :: Get Word48
+getPackedWord48 = getWord48 unpackWord8Word48
+
+word48ToWord64 :: Word48 -> Word64
+word48ToWord64 (Word48 (a,b,c,d,e,f)) = fromIntegral a `shiftL` 40 .|.
+                                        fromIntegral b `shiftL` 32 .|.
+                                        fromIntegral c `shiftL` 24 .|.
+                                        fromIntegral d `shiftL` 16 .|.
+                                        fromIntegral e `shiftL`  8 .|.
+                                        fromIntegral f
+
+-- apply mask and shift result to the very right
+-- TODO: find a laxer type signature
+cutMask :: Integral n => Word64 -> Word64 -> n
+cutMask w mask = fromIntegral . fst $ until p shifter (w .&. mask, mask)
+  where
+    -- shift word by as much as we need to shift the mask to the very right
+    p (x, mask') = mask' `testBit` 0
+    shifter (x, m) = (x `shiftR` 1, m `shiftR` 1)
+