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-rw-r--r--gschem/board.pcb107
-rw-r--r--gschem/outputs.sch94
2 files changed, 100 insertions, 101 deletions
diff --git a/gschem/board.pcb b/gschem/board.pcb
index d1f41b3..0c856ee 100644
--- a/gschem/board.pcb
+++ b/gschem/board.pcb
@@ -6,7 +6,7 @@ FileVersion[20070407]
PCB["" 330000 330000]
Grid[2500.0 0 0 0]
-Cursor[0 0 0.000000]
+Cursor[180000 270000 0.000000]
PolyArea[3100.006200]
Thermal[0.500000]
DRC[1000 1000 1000 1000 1500 1000]
@@ -1515,7 +1515,7 @@ Element["" "TO92" "U501" "unknown" 155000 185000 -13000 -1000 1 100 ""]
)
-Element["" "CONNECTOR-1-2" "CONN301" "unknown" 220000 302500 -21000 5000 1 100 ""]
+Element["" "CONNECTOR-1-2" "CONN301" "unknown" 222500 302500 -21000 5000 1 100 ""]
(
Pin[0 0 6000 3000 6600 3800 "1" "1" "square,edge2,thermal(1X)"]
Pin[-10000 0 6000 3000 6600 3800 "2" "2" "edge2"]
@@ -1624,7 +1624,7 @@ Element["" "TO92_CBE" "Q301" "unknown" 212500 282500 -13000 -1000 1 100 ""]
)
-Element["" "CONNECTOR-2-1" "CONN503" "unknown" 292500 277500 -11000 5000 1 100 ""]
+Element["" "CONNECTOR-2-1" "CONN503" "unknown" 292500 272500 -11000 5000 1 100 ""]
(
Pin[0 0 6000 3000 6600 3800 "1" "1" "square,thermal(1X)"]
Pin[0 -10000 6000 3000 6600 3800 "2" "2" ""]
@@ -1712,7 +1712,7 @@ Element["" "R025" "R430" "1M" 217500 202500 -12000 2000 2 100 ""]
Element["" "R025" "R515" "1M" 217500 187500 -12000 2000 2 100 ""]
(
- Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"]
+ Pin[0 0 6800 3000 7400 3800 "1" "1" "found,square,edge2"]
Pin[-40000 0 6800 3000 7400 3800 "2" "2" "edge2"]
ElementLine [-30000 5000 -10000 5000 2000]
ElementLine [-30000 -5000 -30000 5000 2000]
@@ -1763,7 +1763,7 @@ Element["" "R025" "R516" "100k" 302500 150000 -12000 2000 2 100 ""]
)
-Element["" "R025" "R507" "4k7_???" 262500 165000 12000 -2000 0 100 ""]
+Element["" "R025" "R507" "3k3" 262500 195000 12000 -2000 0 100 ""]
(
Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"]
Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2,thermal(1X)"]
@@ -1776,22 +1776,9 @@ Element["" "R025" "R507" "4k7_???" 262500 165000 12000 -2000 0 100 ""]
)
-Element["" "R025" "R506" "100k" 262500 195000 12000 -2000 0 100 ""]
-(
- Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"]
- Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"]
- ElementLine [10000 -5000 30000 -5000 2000]
- ElementLine [30000 -5000 30000 5000 2000]
- ElementLine [10000 5000 30000 5000 2000]
- ElementLine [10000 -5000 10000 5000 2000]
- ElementLine [0 0 10000 0 2000]
- ElementLine [30000 0 40000 0 2000]
-
- )
-
-Element["" "R025" "R508" "100k" 262500 180000 12000 -2000 0 100 ""]
+Element["" "R025" "R506" "100k" 262500 180000 12000 -2000 0 100 ""]
(
- Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"]
+ Pin[0 0 6800 3000 7400 3800 "1" "1" "found,square,edge2"]
Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"]
ElementLine [10000 -5000 30000 -5000 2000]
ElementLine [30000 -5000 30000 5000 2000]
@@ -1828,7 +1815,7 @@ Element["" "R025" "R307" "4k7" 280000 127500 -12000 2000 2 100 ""]
)
-Element["" "R025" "R520" "100" 275000 267500 -12000 2000 2 100 ""]
+Element["" "R025" "R520" "100" 275000 262500 -12000 2000 2 100 ""]
(
Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"]
Pin[-40000 0 6800 3000 7400 3800 "2" "2" "edge2"]
@@ -1851,16 +1838,6 @@ Element["" "TO92" "Q302" "unknown" 230000 155000 1000 -13000 0 100 ""]
)
-Element["" "TO92" "Q501" "unknown" 240000 195000 -13000 -1000 1 100 ""]
-(
- Pin[0 -20000 7200 3000 7800 4200 "D" "1" "square"]
- Pin[0 -10000 7200 3000 7800 4200 "S" "2" ""]
- Pin[0 0 7200 3000 7800 4200 "G" "3" ""]
- ElementLine [-7000 -17000 -7000 -3000 1000]
- ElementArc [0 -10000 10000 10000 45 270 1000]
-
- )
-
Element["" "TO92_CBE" "Q401" "unknown" 250000 215000 -1000 13000 2 100 ""]
(
Pin[-20000 0 7200 3000 7800 4200 "C" "1" "square,edge2"]
@@ -1884,7 +1861,7 @@ Element["" "R025" "J1" "unknown" 177500 217500 12000 -2000 0 100 ""]
)
-Element["" "CK06_type_capacitor" "C512" "47nF" 260000 252500 -37000 -14400 0 150 ""]
+Element["" "CK06_type_capacitor" "C512" "47nF" 260000 247500 -37000 -14400 0 150 ""]
(
Pin[0 0 8000 3000 11000 3500 "1" "1" "edge2,thermal(1X,5)"]
Pin[-20000 0 8000 3000 11000 3500 "2" "2" "edge2,thermal(4)"]
@@ -1905,6 +1882,29 @@ Element["" "RCY150P" "C510" "220uF" 217500 247500 -15000 -22500 1 100 ""]
ElementArc [0 -7500 15000 15000 90 360 1000]
)
+
+Element["" "TO92_CBE" "Q501" "unknown" 240000 195000 -13000 -1000 1 100 ""]
+(
+ Pin[0 -20000 7200 3000 7800 4200 "1" "1" "square"]
+ Pin[0 -10000 7200 3000 7800 4200 "2" "2" ""]
+ Pin[0 0 7200 3000 7800 4200 "3" "3" ""]
+ ElementLine [-7000 -17000 -7000 -3000 1000]
+ ElementArc [0 -10000 10000 10000 45 270 1000]
+
+ )
+
+Element["" "R025" "R508" "100k" 262500 165000 12000 -2000 0 100 ""]
+(
+ Pin[0 0 6800 3000 7400 3800 "1" "1" "square,edge2"]
+ Pin[40000 0 6800 3000 7400 3800 "2" "2" "edge2"]
+ ElementLine [10000 -5000 30000 -5000 2000]
+ ElementLine [30000 -5000 30000 5000 2000]
+ ElementLine [10000 5000 30000 5000 2000]
+ ElementLine [10000 -5000 10000 5000 2000]
+ ElementLine [0 0 10000 0 2000]
+ ElementLine [30000 0 40000 0 2000]
+
+ )
Layer(1 "component")
(
Line[177500 217500 217500 217500 2000 2000 "clearline"]
@@ -2008,7 +2008,7 @@ Layer(2 "solder")
Line[247500 52500 252500 57500 2000 2000 "clearline"]
Line[290000 47500 280000 37500 2000 2000 "clearline"]
Line[257500 37500 280000 37500 2000 2000 "clearline"]
- Line[287500 90000 287500 180000 2000 2000 "clearline"]
+ Line[287500 90000 287500 165000 2000 2000 "clearline"]
Line[290000 87500 287500 90000 2000 2000 "clearline"]
Line[290000 87500 290000 67500 2000 2000 "clearline"]
Line[62500 177500 52500 187500 2000 2000 "clearline"]
@@ -2107,8 +2107,6 @@ Layer(2 "solder")
Line[212500 272500 210000 272500 2000 2000 "clearline"]
Line[195000 287500 197500 287500 2000 2000 "clearline"]
Line[210000 272500 195000 257500 2000 2000 "clearline"]
- Line[210000 302500 210000 285000 2000 2000 "clearline"]
- Line[210000 285000 212500 282500 2000 2000 "clearline"]
Line[235000 302500 235000 287500 2000 2000 "clearline"]
Line[212500 282500 230000 282500 2000 2000 "clearline"]
Line[230000 282500 235000 287500 2000 2000 "clearline"]
@@ -2119,30 +2117,20 @@ Layer(2 "solder")
Line[192500 170000 192500 235000 2000 2000 "clearline"]
Line[197500 237500 197500 177500 2000 2000 "clearline"]
Line[202500 185000 202500 240000 2000 2000 "clearline"]
- Line[270000 115000 270000 157500 2000 2000 "clearline"]
Line[177500 172500 177500 202500 2000 2000 "clearline"]
Line[202500 172500 197500 177500 2000 2000 "clearline"]
Line[207500 180000 202500 185000 2000 2000 "clearline"]
Line[145000 185000 155000 185000 2000 2000 "clearline"]
Line[292500 115000 300000 107500 2000 2000 "clearline"]
- Line[302500 195000 287500 180000 2000 2000 "clearline"]
- Line[302500 180000 300000 180000 2000 2000 "clearline"]
- Line[292500 170000 302500 180000 2000 2000 "clearline"]
Line[305000 150000 310000 155000 2000 2000 "clearline"]
- Line[292500 170000 292500 115000 2000 2000 "clearline"]
- Line[262500 180000 262500 195000 2000 2000 "clearline"]
+ Line[292500 155000 292500 115000 2000 2000 "clearline"]
Line[302500 150000 302500 120000 2000 2000 "clearline"]
Line[302500 120000 300000 117500 2000 2000 "clearline"]
Line[270000 210000 290000 230000 2000 2000 "clearline"]
Line[310000 155000 310000 220000 2000 2000 "clearline"]
Line[310000 220000 300000 230000 2000 2000 "clearline"]
Line[172500 270000 202500 240000 2000 2000 "clearline,rubberend"]
- Line[212500 262500 196250 246250 2000 2000 "clearline"]
Line[202500 172500 217500 172500 2000 2000 "clearline"]
- Line[270000 157500 252500 175000 2000 2000 "clearline"]
- Line[252500 175000 252500 180000 2000 2000 "clearline,rubberend"]
- Line[252500 180000 247500 185000 2000 2000 "clearline"]
- Line[247500 185000 240000 185000 2000 2000 "clearline,rubberend"]
Line[207500 180000 235000 180000 2000 2000 "clearline"]
Line[177500 187500 157500 187500 2000 2000 "clearline"]
Line[157500 187500 155000 185000 2000 2000 "clearline"]
@@ -2151,8 +2139,6 @@ Layer(2 "solder")
Line[230000 155000 230000 160000 2000 2000 "clearline"]
Line[230000 160000 217500 172500 2000 2000 "clearline"]
Line[240000 145000 240000 155000 2000 2000 "clearline"]
- Line[225000 195000 217500 187500 2000 2000 "clearline"]
- Line[225000 195000 262500 195000 2000 2000 "clearline"]
Line[217500 202500 235000 202500 2000 2000 "clearline"]
Line[240000 207500 235000 202500 2000 2000 "clearline"]
Line[177500 217500 185000 217500 2000 2000 "clearline"]
@@ -2162,19 +2148,32 @@ Layer(2 "solder")
Line[240000 207500 240000 217500 2000 2000 "clearline"]
Line[240000 217500 252500 230000 2000 2000 "clearline"]
Line[252500 230000 262500 230000 2000 2000 "clearline"]
- Line[275000 267500 292500 267500 2000 2000 "clearline"]
+ Line[275000 262500 292500 262500 2000 2000 "clearline"]
Line[212500 262500 230000 262500 2000 2000 "clearline"]
- Line[230000 262500 235000 267500 2000 2000 "clearline"]
+ Line[230000 262500 235000 262500 2000 2000 "clearline"]
Line[217500 247500 217500 257500 2000 2000 "clearline"]
Line[217500 257500 212500 262500 2000 2000 "clearline"]
- Line[240000 252500 240000 262500 2000 2000 "clearline"]
- Line[240000 262500 235000 267500 2000 2000 "clearline"]
Line[272500 230000 292500 250000 2000 2000 "clearline"]
Line[255000 210000 270000 210000 2000 2000 "clearline"]
Line[205000 217500 227500 217500 2000 2000 "clearline"]
Line[227500 217500 230000 215000 2000 2000 "clearline"]
Line[240000 145000 240000 120000 2000 2000 "clearline"]
Line[240000 120000 252500 107500 2000 2000 "clearline"]
+ Line[217500 187500 237500 187500 2000 2000 "clearline"]
+ Line[237500 187500 240000 185000 2000 2000 "clearline"]
+ Line[262500 165000 262500 180000 2000 2000 "clearline"]
+ Line[292500 155000 302500 165000 2000 2000 "clearline"]
+ Line[302500 165000 300000 165000 2000 2000 "clearline"]
+ Line[302500 180000 287500 165000 2000 2000 "clearline"]
+ Line[240000 185000 257500 185000 2000 2000 "clearline"]
+ Line[257500 185000 262500 180000 2000 2000 "clearline"]
+ Line[262500 195000 240000 195000 2000 2000 "clearline"]
+ Line[270000 115000 270000 187500 2000 2000 "clearline"]
+ Line[270000 187500 262500 195000 2000 2000 "clearline"]
+ Line[235000 262500 235000 252500 2000 2000 "clearline"]
+ Line[235000 252500 240000 247500 2000 2000 "clearline"]
+ Line[212500 262500 196250 246250 2000 2000 "clearline"]
+ Line[212500 302500 212500 282500 2000 2000 "clearline,selected"]
Polygon("clearpoly")
(
[0 0] [330000 0] [330000 330000] [0 330000]
@@ -2515,7 +2514,7 @@ NetList()
)
Net("unnamed_net33" "(unknown)")
(
- Connect("Q501-3")
+ Connect("Q501-2")
Connect("R506-1")
Connect("R508-1")
Connect("R515-1")
@@ -2523,7 +2522,7 @@ NetList()
Net("unnamed_net34" "(unknown)")
(
Connect("C508-1")
- Connect("Q501-2")
+ Connect("Q501-3")
Connect("R507-1")
)
Net("unnamed_net35" "(unknown)")
diff --git a/gschem/outputs.sch b/gschem/outputs.sch
index b07de56..12d8791 100644
--- a/gschem/outputs.sch
+++ b/gschem/outputs.sch
@@ -59,8 +59,8 @@ value=100k
T 51000 45700 5 10 0 1 0 0 1
footprint=R025
}
-N 51600 45200 52800 45200 4
-N 53200 44800 54600 44800 4
+N 51600 45200 52700 45200 4
+N 53200 44500 54600 44500 4
C 51000 44900 1 180 0 resistor-2.sym
{
T 50600 44550 5 10 0 0 180 0 1
@@ -85,34 +85,34 @@ device=none
T 47500 44800 5 10 1 1 0 7 1
value=from B Jack switch
}
-C 54600 44600 1 0 0 capacitor-4.sym
+C 54600 44300 1 0 0 capacitor-4.sym
{
-T 54800 45700 5 10 0 0 0 0 1
+T 54800 45400 5 10 0 0 0 0 1
device=POLARIZED_CAPACITOR
-T 54800 45100 5 10 1 1 0 0 1
+T 54800 44800 5 10 1 1 0 0 1
refdes=C508
-T 54800 45300 5 10 0 0 0 0 1
+T 54800 45000 5 10 0 0 0 0 1
symversion=0.1
-T 54600 44600 5 10 1 1 0 0 1
+T 54600 44300 5 10 1 1 0 0 1
value=1u
-T 54600 44600 5 10 0 1 0 0 1
+T 54600 44300 5 10 0 1 0 0 1
footprint=RCY100P
}
-C 55700 44500 1 270 0 resistor-2.sym
+C 55700 44200 1 270 0 resistor-2.sym
{
-T 56050 44100 5 10 0 0 270 0 1
+T 56050 43800 5 10 0 0 270 0 1
device=RESISTOR
-T 56000 44000 5 10 1 1 0 0 1
+T 56000 43700 5 10 1 1 0 0 1
refdes=R514
-T 56000 43800 5 10 1 1 0 0 1
+T 56000 43500 5 10 1 1 0 0 1
value=100k
-T 55700 44500 5 10 0 1 0 0 1
+T 55700 44200 5 10 0 1 0 0 1
footprint=R025
}
-C 55500 42800 1 0 0 vcc-minus-1.sym
-N 55500 44800 56800 44800 4
-N 55800 44800 55800 44500 4
-N 55800 43600 55800 43400 4
+C 55500 42500 1 0 0 vcc-minus-1.sym
+N 55500 44500 56800 44500 4
+N 55800 44500 55800 44200 4
+N 55800 43300 55800 43100 4
T 47300 42000 9 10 1 0 0 0 8
When there's no cable connected to output B,
the blended bass signal lies on JACKSWITCH_B:1.
@@ -122,13 +122,13 @@ to one mono signal.
When a cable is connected, i.e. when stereo
output is requested, there is no signal on
JACKSWITCH_B:1.
-C 56800 44000 1 0 0 connector2-2.sym
+C 56800 43700 1 0 0 connector2-2.sym
{
-T 57500 45300 5 10 1 1 0 6 1
+T 57500 45000 5 10 1 1 0 6 1
refdes=CONN501
-T 57100 45250 5 10 0 0 0 0 1
+T 57100 44950 5 10 0 0 0 0 1
device=CONNECTOR_2
-T 57100 45450 5 10 0 0 0 0 1
+T 57100 45150 5 10 0 0 0 0 1
footprint=CONNECTOR 2 1
}
C 53400 48500 1 0 0 connector3-2.sym
@@ -140,10 +140,10 @@ device=CONNECTOR_3
T 53700 50350 5 10 0 0 0 0 1
footprint=CONNECTOR 3 1
}
-C 56300 42800 1 0 0 vcc-minus-1.sym
-N 56800 44400 56600 44400 4
-N 56600 44400 56600 43400 4
-T 56600 45700 9 10 1 0 0 0 1
+C 56300 42500 1 0 0 vcc-minus-1.sym
+N 56800 44100 56600 44100 4
+N 56600 44100 56600 43100 4
+T 56600 45500 9 10 1 0 0 0 1
A/Mono out
C 51600 49200 1 0 0 input-2.sym
{
@@ -212,31 +212,22 @@ N 61700 44400 61700 44500 4
B 59800 43300 6500 5600 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
T 59900 49000 9 10 1 0 0 0 1
Virtual ground and power supply filtering
-C 52800 45000 1 0 0 JFET_N-Channel-1.sym
+C 53100 44400 1 270 0 resistor-2.sym
{
-T 53150 45800 5 10 1 1 0 6 1
-refdes=Q501
-T 52800 47050 5 10 0 0 0 0 1
-device=JFET N-Channel
-T 52800 45000 5 10 0 0 0 0 1
-footprint=TO92
-}
-C 53100 44700 1 270 0 resistor-2.sym
-{
-T 53450 44300 5 10 0 0 270 0 1
+T 53450 44000 5 10 0 0 270 0 1
device=RESISTOR
-T 53400 44200 5 10 1 1 0 0 1
+T 53400 43900 5 10 1 1 0 0 1
refdes=R507
-T 53400 44000 5 10 1 1 0 0 1
-value=4k7 ???
-T 53100 44700 5 10 0 1 0 0 1
+T 53400 43700 5 10 1 1 0 0 1
+value=3k3
+T 53100 44400 5 10 0 1 0 0 1
footprint=R025
}
-C 53000 46300 1 0 0 vcc-2.sym
-N 53200 46300 53200 45800 4
-N 53200 45000 53200 44700 4
-C 52900 42800 1 0 0 vcc-minus-1.sym
-N 53200 43400 53200 43800 4
+C 53000 46200 1 0 0 vcc-2.sym
+N 53200 46200 53200 45700 4
+N 53200 44700 53200 44400 4
+C 52900 42500 1 0 0 vcc-minus-1.sym
+N 53200 43100 53200 43500 4
C 52100 44700 1 270 0 resistor-2.sym
{
T 52450 44300 5 10 0 0 270 0 1
@@ -248,9 +239,9 @@ value=1M
T 52100 44700 5 10 0 1 0 0 1
footprint=R025
}
-C 52100 42900 1 0 0 gnd-1.sym
+C 52100 42600 1 0 0 gnd-1.sym
N 52200 44700 52200 45200 4
-N 52200 43200 52200 43800 4
+N 52200 42900 52200 43800 4
C 62900 44500 1 90 0 capacitor-1.sym
{
T 62200 44700 5 10 0 0 90 0 1
@@ -319,3 +310,12 @@ footprint=R025
N 50300 49700 50300 49300 4
C 50000 47700 1 0 0 vcc-minus-1.sym
N 50300 48300 50300 48400 4
+C 52700 44700 1 0 0 bc550.sym
+{
+T 53300 45200 5 10 0 0 0 0 1
+device=NPN_TRANSISTOR
+T 53300 45200 5 10 1 1 0 0 1
+refdes=Q501
+T 52700 44700 5 10 0 0 0 0 1
+footprint=TO92_CBE
+}
generated by cgit v1.2.3 (git 2.46.0) at 2024-11-09 23:05:00 +0000