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| author | Friedrich Beckmann <friedrich.beckmann@gmx.de> | 2016-02-28 17:04:09 +1100 |
|---|---|---|
| committer | Lars Ingebrigtsen <larsi@gnus.org> | 2016-02-28 17:04:09 +1100 |
| commit | 0d60bfc431e1abe2f5b1c5e47acd0922f8708476 (patch) | |
| tree | 7981be6ee15f2cb343c442bbb740f3e7319f4af6 | |
| parent | 5cac11aa0676416432efca82e352938d4d4366f3 (diff) | |
Fix ModelSim error parsing
* lisp/progmodes/vhdl-mode.el (vhdl-compiler-alist): Fix
ModelSim error parsing (bug#5768).
Copyright-paperwork-exempt: yes
| -rw-r--r-- | lisp/progmodes/vhdl-mode.el | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lisp/progmodes/vhdl-mode.el b/lisp/progmodes/vhdl-mode.el index 5c78aaa1da..27ce9fb1b3 100644 --- a/lisp/progmodes/vhdl-mode.el +++ b/lisp/progmodes/vhdl-mode.el @@ -266,9 +266,14 @@ Overrides local variable `indent-tabs-mode'." ;; WARNING[2]: test.vhd(85): Possible infinite loop ;; ** Warning: [4] ../src/emacsvsim.vhd(43): An abstract ... ;; ** Error: adder.vhd(190): Unknown identifier: ctl_numb + ;; ** Error: counter_rtl.vhd(18): Nonresolved signal 'hallo' has multiple sources. + ;; Drivers: + ;; counter_rtl.vhd(27):Conditional signal assignment line__27 + ;; counter_rtl.vhd(29):Conditional signal assignment line__29 ("ModelSim" "vcom" "-93 -work \\1" "make" "-f \\1" nil "vlib \\1; vmap \\2 \\1" "./" "work/" "Makefile" "modelsim" - ("^\\(ERROR\\|WARNING\\|\\*\\* Error\\|\\*\\* Warning\\)[^:]*:\\( *\\[[0-9]+]\\)? \\([^ \t\n]+\\)(\\([0-9]+\\)):" 3 4 nil) ("" 0) + ("\\(ERROR:\\|WARNING\\[[0-9]+\\]:\\|\\*\\* Error:\\|\\*\\* Warning: \\[[0-9]+\\]\\| +\\) \\([^ ]+\\)(\\([0-9]+\\)):" 2 3 nil) + ("" 0) ("\\1/_primary.dat" "\\2/\\1.dat" "\\1/_primary.dat" "\\1/_primary.dat" "\\1/body.dat" downcase)) ;; ProVHDL, Synopsys LEDA: provhdl -w work -f test.vhd |